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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos logdac dual logarithmic d/a converter ad7112* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram 17-bit dac a ad7112 out a agnd dgnd cs wr 17-bit latch 17 17-bit latch 17-bit dac b r fb a out b r fb b decode logic v in b v in a dac a/ dac b control logic 8-bit buffer db0 db7 v dd features dynamic range: 88.5 db resolution: 0.375 db on-chip data latches for both dacs four-quadrant multiplication +5 v operation pin compatible with ad7528 low power applications audio attenuators sonar systems function generators general description the logdac? ad7112 is a monolithic dual multiplying d/a converter featuring wide dynamic range and excellent dac-to- dac matching. both dacs can attenuate an analog input sig- nal over the range 0 db to 88.5 db in 0.375 db steps. it is available in skinny 0.3" wide 20-pin dips and in 20-terminal surface mount packages. the degree of attenuation in either channel is determined by the 8-bit word applied to the onboard decode logic. this 8-bit word is decoded into a 17-bit word which is then loaded into one of the 17-bit data latches, determined by daca /dacb. the fine step resolution over the entire dynamic range is due to the use of these 17-bit dacs. the ad7112 is easily interfaced to a standard 8-bit mpu bus via an 8-bit data port and standard microprocessor control lines. it should be noted that the ad7112 is exactly pin-compatible with the ad7528, an industry standard dual 8-bit multiplying dac. this allows an easy upgrading of existing ad7528 de- signs which would benefit both from the wider dynamic range and the finer step resolution offered by the ad7112. the ad7112 is fabricated in linear compatible cmos (lc 2 mos), an advanced, mixed technology process that com- bines precision bipolar circuits with low power cmos logic. * protected by u.s. patent no. 4521764. logdac is a registered trademark of analog devices, inc. product highlights 1. dac-to-dac matching: since both of the ad7112 dacs are fabricated at the same time on the same chip, precise matching and tracking between the two dacs is inherent. 2. small package: the ad7112 is available in a 20-pin dip and a 20-terminal soic package. 3. fast microprocessor interface: the ad7112 has bus inter- face timing compatible with all modern microprocessors.
rev. 0 C2C ad7112Cspecifications (v dd = +5 v 6 5%; out a = out b = agnd = dgnd = 0 v; v in a = v in b = 10 v. output amplifier ad712 except where noted. all specifications t min to t max unless otherwise noted.) c version 1 b version t a =t a =t a =t a = parameter +25 8 ct min , t max +25 8 ct min , t max units conditions/comments accuracy resolution 0.375 0.375 0.375 0.375 db accuracy relative to guaranteed attenuation 0 db attenuation ranges for specified step sizes. 0.375 db steps: accuracy 0.17 db 0 to 36 0 to 36 0 to 30 0 to 30 db min monotonic 0 to 54 0 to 54 0 to 48 0 to 48 db min 0.75 db steps: accuracy 0.35 db 0 to 48 0 to 42 0 to 42 0 to 36 db min monotonic 0 to 72 0 to 66 0 to 72 0 to 60 db min 1.5 db steps: accuracy 0.7 db 0 to 54 0 to 48 0 to 48 0 to 42 db min monotonic full range 0 to 78 0 to 85.5 0 to 72 db min full range is 0 db to 88.5 db. 3.0 db steps: accuracy 1.4 db 0 to 66 0 to 54 0 to 60 0 to 48 db min monotonic full range full range full range full range db min 6.0 db steps: accuracy 2.7 db 0 to 72 0 to 60 0 to 60 0 to 60 db min monotonic full range full range full range full range db min gain error 0.1 0.15 0.15 0.2 db max measured using r fb a, r fb b. both dac registers loaded with all 0s. output leakage current out a, out b 50 400 50 400 na max input resistance, v in a, v in b 9/15 9/15 9/15 9/15 k w min/max typically 12 k w . input resistance match 1 1 2 2 % max feedback resistance, r fb a, r fb b 9.3/15.7 9.3/15.7 9.3/15.7 9.3/15.7 k w min/max logic inputs cs , wr , dac a /dac b, db0Cdb7 input low voltage, v inl 0.8 0.8 0.8 0.8 v max input high voltage, v inh 2.4 2.4 2.4 2.4 v min input leakage current 1 10 1 10 m a max input capacitance 2 10 10 10 10 pf max power requirements v dd , range 3 4.75/5.25 4.75/5.25 4.75/5.25 4.75/5.25 v min/max for specified performance. 2 2 2 2 ma max logic inputs = v il or v ih 2 2 2 2 ma max logic inputs = 0 v or v dd notes l temperature range as follows: b, c versions: C40 c to +85 c. 2 guaranteed by design, not production tested. 3 the part will function with v dd = 5 v 10% with degraded performance. specifications subject to change without notice.
ad7112 rev. 0 C3C timing specifications 1 parameter t a = +25 8 ct a = C40 8 c to +85 8 c units conditions/comments cs to wr setup time t cs 0 0 ns min see figure 3. cs to wr hold time t ch 0 0 ns min dac select to wr setup time t as 4 4 ns min dac select to wr hold time t ah 0 0 ns min data valid to wr setup time t ds 55 55 ns min data valid to wr hold time t dh 10 10 ns min wr pulse width t wr 53 53 ns min notes 1 timing specifications guaranteed by design not production tested. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. specifications subject to change without notice. ac performance characteristics 1 t a = t a = C40 8 c to parameter +25 8 c +85 8 c units conditions/comments dc supply rejection d gain/ d v dd 0.001 0.005 db/% max d v dd = 5%. input code = 00000000 digital-to-analog glitch impulse 10 10 nv s typ measured with ad843 as output amplifier for input code transition 10000000 to 00000000. output capacitance, c out a , c out b 50 50 pf max ac feedthrough v in a to out a C94 C90 db max v in a, v in b = 6 v rms at 1 khz. dac registers loaded with all 1s. v in b to out b C94 C90 db max channel-to-channel isolation v in a to out b C87 C87 db typ v in a = 6 v rms at 10 khz sine wave, v in b = 0 v. dac registers loaded with all 0s. v in b to out a C87 C87 db typ v in b = 6 v rms at 10 khz sine wave, v in a = 0 v. dac registers loaded with all 0s. digital feedthrough 1 1 nv s typ me asured with input code transitions of all 0s to all 1s. output noise voltage density (30 hz to 50 khz) 15 15 nv/ ? hz typ measured between r fb a and out a or between r fb b and out b. total harmonic distortion C91 C91 db typ v in a = v in b = 6 v rms at 1 khz. dac registers loaded with all 0s. notes 1 guaranteed by design, not production tested. specifications subject to change without notice. (v dd = +5 v 6 5%; 0ut a = out b = agnd = dgnd = o v; v in a = v in b = 10 v) (v dd = +5 v 6 5%; 0ut a = out b = agnd = dgnd = 0 v; v in a = v in b = 10 v. output amplifier ad712 except where noted.)
ad7112 rev. 0 C4C absolute maximum ratings* v dd to agnd or dgnd . . . . . . . . . . . . . . . . . . C0.3 v, +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v digital inputs to dgnd . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v out a, out b to agnd . . . . . . . . . . . C0.3 v, v dd + 0.3 v v in a, v in b to agnd . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfb a, v rfb b to agnd . . . . . . . . . . . . . . . . . . . . . . . 25 v operating temperature range all versions . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . C65 c to +150 c power dissipation, dip . . . . . . . . . . . . . . . . . . . . . . . . . . 1 w q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 102 c/w lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c power dissipation, soic . . . . . . . . . . . . . . . . . . . . . . . . . 1 w q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature (soldering) vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7112 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. terminology resolution: nominal change in attenuation when moving between two adjacent codes. monotonicity: the device is monotonic if the analog out- put decreases or remains constant as the wdigital code in- creases. feedthrough error: that portion of the input signal which reaches the output when all digital inputs are high. output capacitance: capacitance from out a or out b to ground. gain error: gain error results from a mismatch between r fb (the feedback resistance) and the r-2r ladder resistance. its effect in a logdac is to produce a constant additive at- tenuation error in db over the whole range of the dac. accuracy: the difference (measured in db) between the ideal transfer function as listed in table i and the actual trans- fer function as measured with the device. digital-to-analog glitch impulse: the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-s or nv-s depending on whether the glitch is measured as a current or voltage signal. glitch im- pulse is measured with v in = agnd. ordering information specified temperature accuracy package model range range option* ad7112bn C40 c to +85 c 0 db to 60 db n-20 ad7112cn C40 c to +85 c 0 db to 72 db n-20 ad7112br C40 c to +85 c 0 db to 60 db r-20 ad7112cr C40 c to +85 c 0 db to 72 db r-20 *n = plastic dip; r = soic. pin function description pin mnemonic description 1 agnd analog ground. 2 out a current output terminal of dac a. 3r fb a feedback resistor for dac a. 4v in a reference input to dac a 5 dgnd digital ground. 6 dac a / selects which dac can accept data from dac b input port. 7C14 db7Cdb0 8 data inputs. 15 cs chip select input, active low. 16 wr write input, active low. 17 v dd power supply input 5 v 5%. 18 v in b reference input to dac b. 19 r fb b feedback resistor for dac b. 20 out b current output terminal of dac b. pin configuration dip/soic agnd out a dgnd (msb) db7 dac a/dac b db6 db5 db4 r fb a v in a out b r fb b v in b v dd db0 (lsb) db1 db2 db3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 top view (not to scale) ad7112 wr cs
ad7112 rev. 0 C5C circuit description general circuit information the ad7112 consists of a dual 17-bit r-2r cmos multiplying d/a converter with extensive digital logic. figure 1 shows a sim- plified circuit of the d/a converter section of the ad7112. the logic translates the 8-bit binary input into a 17-bit word which is used to drive the d/a converter. figure 2 shows a typical circuit configuration for the ad7112. the transfer function for the circuit of figure 2 is given by: v o = v in 10 exp 0.375 n 20 or v o v in db = 0.375 n where 0.375 is the step size (resolution ) in db and n is the input code in decimal for values 0 to 239. for 240 n 255 the output is zero. table i gives the output attenuation relative to 0 db for all possible input codes. r 2r v in a rr 2r 2r 2r 2r r r fb a out a agnd s1 s2 s3 s17 figure 1. simplified d/a circuit of 1/2 ad7112 figures 16 and 17 give a pictorial representation of the specified accuracy and monotonic ranges for all grades of the ad7112. high attenuation levels are specified with less accuracy than low attenuation levels. the range of monotonic behavior depends upon the attenuation step size used. to achieve monotonic op- eration over the entire 88.5 db range, it is necessary to select in- put codes so that the attenuation step size at any point is consistent with the step size guaranteed for monotonic opera- tion at that point. out a agnd dac a ad7112 dgnd cs wr r fb a v in a dac a/dac b v dd 15 4 3 17 5 2 1 v out a1 c1 signal ground a1: 1/2 ad712 1/2 op-275 6 16 notes 1. only one dac is shown for clarity. 2. data input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier. figure 2. typical circuit configuration table i. ideal attenuation in db vs. input code d7Cd4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 0001 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 0010 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 0011 18.000 18.375 18.750 19.125 19.500 19.875 20.250 20.625 21.000 21.375 21.750 22.125 22.500 22.875 23.250 23.625 0100 24.000 24.375 24.750 25.125 25.500 25.875 26.250 26.625 27.000 27.375 27.750 28.125 28.500 28.875 29.250 29.625 0101 30.000 30.375 30.750 31.125 31.500 31.875 32.250 32.625 33.000 33.375 33.750 34.125 34.500 34.875 35.250 35.625 0110 36.000 36.375 36.750 37.125 37.500 37.875 38.250 38.625 39.000 39.375 39.750 40.125 40.500 40.875 41.250 41.625 0111 42.000 42.375 42.750 43.125 43.500 43.875 44.250 44.625 45.000 45.375 45.750 46.125 46.500 46.875 47.250 47.625 1000 48.000 48.375 48.750 49.125 49.500 49.875 50.250 50.625 51.000 51.375 51.750 52.125 52.500 52.875 53.250 53.625 1001 54.000 54.375 54.750 55.125 55.500 55.875 56.250 56.625 57.000 57.375 57.750 58.125 58.500 58.875 59.250 59.625 1010 60.000 60.375 60.750 61.125 61.500 61.875 62.250 62.625 63.000 63.375 63.750 64.125 64.500 64.875 65.250 65.625 1011 66.000 66.375 66.750 67.125 67.500 67.875 68.250 68.625 69.000 69.375 69.750 70.125 70.500 70.875 71.250 71.625 1100 72.000 72.375 72.750 73.125 73.500 73.875 74.250 74.625 75.000 75.375 75.750 76.125 76.500 76.875 77.250 77.625 1101 78.000 78.375 78.750 79.125 79.500 79.875 80.250 80.625 81.000 81.375 81.750 82.125 82.500 82.875 83.250 83.625 1110 84.000 84.375 84.750 85.125 85.500 85.875 86.250 86.625 87.000 87.375 87.750 88.125 88.500 88.875 89.250 89.625 1111 mute mute mute mute mute mute mute mute mute mute mute mute mute mute mute mute d3Cd0
ad7112 rev. 0 C6C interface logic information dac selection both dac latches share a common 8-bit port. the control in- put dac a /dac b selects which dac can accept data from the input port. mode selection inputs cs and wr control the operating mode of the selected dac. see the mode selection table below. write mode when cs and wr are both low the dac is in the write mode. the input data latches of the selected dac are transparent and its analog output responds to activity on db0Cdb7. hold mode the selected dac latch retains the data which was present on db0Cdb7 just prior to cs and wr assuming a high state. both analog outputs remain at the values corresponding to the data in their respective latches. mode selection table daca / dac b cs wr dac a dac b l l l write hold h l l hold write x h x hold hold x x h hold hold l = low state, v il ; h = high state, v ih ; x = dont care. t as dac a/dac b t ah t wr t ds v ih v il t dh t cs t ch db0?b7 cs wr notes 1. all input signal rise and fall times measured from 10% to 90% of v dd . t r = t f = 20ns. 2. control timing measurement reference level = (v ih + v il ) / 2 figure 3. write cycle timing diagram dynamic performance the dynamic performance of the ad7112 will depend on the gain and phase characteristics of the output amplifier, together with the optimum choice of pc board layout and decoupling components. circuit layout is most important if the optimum performance of the ad7112 is to be achieved. most application problems stem from either poor layout, grounding errors, or in- appropriate choice of amplifier. ensure that the layout of the printed circuit board has the digital and analog lines separated as much as possible. take care not to run any digital track alongside an analog signal track. establish a single point analog ground (star ground) separate from the logic system ground. place this ground as close as possible to the ad7112. connect all analog grounds to this star ground, and also connect the ad7112 dgnd to this ground. do not connect any other digi- tal grounds to this analog ground point. low impedance analog and digital power supply common returns are essential for low noise and high performance of these converters, therefore the foil width of these tracks should be as wide as possible. the use of ground planes is recommended as this minimizes impedance paths and also guards the analog circuitry from digital noise. it is recommended that when using the ad7112 with a high speed amplifier, a capacitor (c1) be connected in the feedback path as shown in figure 2. this capacitor which should be be- tween 5 pf and 15 pf, compensates for the phase lag intro- duced by the output capacitance of the d/a converter. figures 4 and 5 show the performance of the ad7112 using the ad712, a high speed, low cost bifet amplifier, and the op275, a dual bipolar/jfet amplifier suitable for audio appli- cations. the performance with and without the compensation capacitor is shown in both cases. for operation beyond 250 khz, capacitor c1 may be reduced in value. this gives an increase in bandwidth at the expense of a poorer transient re- sponse as shown in figure 7. in circuits where c1 is not in- cluded, the high frequency roll-off point is primarily determined by the characteristics of the output amplifier and not the ad7112. feedthrough and accuracy are sensitive to output leakage cur- rents effects. for this reason it is recommended that the operat- ing temperature of the ad7112 be kept as close to +25 c as is practically possible, particularly where the devices performance at high attenuation levels is important. a typical plot of leakage current vs. temperature is shown in figure 11. some solder fluxes and cleaning materials can form slightly conductive films which cause leakage effects between analog in- put and output. the user is cautioned to ensure that the manu- facturing process for circuits using the ad7112 does not allow such films to form. otherwise the feedthrough, accuracy and maximum usable range will be affected. static accuracy performance the d/a converter section of the ad7112 consists of a 17-bit rC2r type converter. to obtain optimum static performance at this level of resolution it is necessary to pay great attention to amplifier selection, circuit grounding, etc. amplifier input bias current results in a dc offset at the output of the amplifier due to current flowing in the feedback resistor r fb . it is recommended that amplifiers with input bias currents of less than 10 na be used (e.g., ad712) to minimize this offset.
ad7112 rev. 0 C7C another error arises from the output amplifiers input offset volt- age. the amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the ad7112 output im- pedance) varies as a function of the attenuation level. this has the effect of varying the noise gain of the amplifier thus creating a varying error due to amplifier offset voltage. it is recom- mended that an amplifier with less than 50 m v of input offset be used (such as the ad712 or adop07) in dc applications. am- plifiers with a large input offset voltage may cause audible thumps in audio applications due to dc output changes. the ad7112 accuracy is specified and tested using only the internal feedback resistor. any gain error (i.e., mismatch of r fb to the rC2r ladder) that may exist in the ad7112 d/a converter cir- cuit results in a constant attenuation error over the whole range. the ad7112 accuracy is specified relative to 0 db attenuation, hence gain trim resistors can be used to adjust v out = v in pre- cisely (i.e., 0 db attenuation) with input code 00000000. for further information on gain error refer to the cmos dac ap- plication guide which is available from analog devices, publi- cation number g872b-8-1/89. typical performance characteristics i dd ?ma 6 0 5 3 1 2 0 5 4 34 2 1 v in ?volts t a = +25 c all digital inputs tied together figure 6. supply current vs. logic input level frequency ?hz normalized gain with respect to 1khz op275 c1 = 0pf 10 ?0 10 4 10 7 0 ?0 10 5 ?0 op275 c1 = 15pf ad712 c1 = 0pf ad712 c1 = 15pf 10 6 v dd = +5v t a = +25 c data input code = 0000 0000 v in = 1v rms figure 7. frequency response with ad712 and op275 10 90 100 0% 200ns 5v c1 = 0pf c1 = 15pf data change from 00h to 80h 5v a1 0.8v figure 4. response of ad7112 with ad712 10 90 100 0% 200ns 5v c1 = 0pf c1 = 15pf data change from 00h to 80h 5v a1 0.8v figure 5. response of ad7112 with op275
ad7112 rev. 0 C8C ?0 ?0 ?00 ?0 ?0 10 10 10 10 10 12345 frequency hz total harmonic distortion db op275 ad712 v in = 6v rms input code = 0000 0000 t = +25 c c1 = 15pf figure 8. distortion vs. frequency ?0 ?0 ?00 10 3 10 4 10 6 10 5 ?0 ?0 ?0 ?0 frequency ?hz feedthrough ?db v dd = +5v t = +25 c v in a, v in b = 20v p? sine wave figure 9. feedthrough vs. frequency ?0 ?0 ?00 10 3 10 4 10 6 10 5 ?0 ?0 ?0 ?0 v dd = +5v t a = +25 c v in a = 20v p? sine wave v in b = 0v both dac latches loaded with 0000 0000 frequency ?hz channel-channel isolation ?db figure 10. channel-to-channel isolation vs. frequency 2 0 ?0 85 ?5 1 35 60 10 temperature ? c output leakage current i out ?na v dd = +5v v in = ?0v data input = 1111 xxxx figure 11. output leakage current vs. temperature ad712 output data inputs from 00h to 80h 10 90 100 0% 200ns 5v 10mv a1 2.0v v dd = +5v t a = +25 c v in = agnd figure 12. digital-to-analog glitch impulse frequency ?hz 50 30 10 10 2 10 3 10 5 10 4 v dd = +5v v in = 0v dac code = 0000 0000 includes op275 amplifier noise 20 40 noise spectral density ?nv/ hz figure 13. noise spectral density vs. frequency
ad7112 rev. 0 C9C * 0.4 ?.6 30 0.0 ?.4 3 ?.2 0 0.2 27 24 21 18 15 12 9 6 attenuation ?db error ?db * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *** * * * * * * * v dd = +5v t a = +25 c figure 14. typical attenuation error for 0.75 db steps 1.0 ?.0 078 0.5 ?.5 6 0.0 66 72 60 48 42 36 30 24 18 12 54 84 attenuation ?db error ?db t a = +25 c t a = +85 c v dd = +5v figure 15. typical attenuation error for 3 db steps vs. temperature aaaaaaa aaaaaaa aaaaa 1 ? 0 90 2 ? 6 0 78 84 72 66 60 54 18 12 48 42 36 30 24 attenuation ?db error ?db +0.17 ?.17 85.5 0.375 db attenuation steps monotonicity for 1.5 db attenuation steps 0.75 db attenuation steps figure 16. accuracy specification for b grade devices at t a = +25 c 1 ? 0 90 2 ? 6 0 78 84 72 66 60 54 18 12 48 42 36 30 24 attenuation ?db error ?db +0.17 ?.17 aaaaaaa aaaaaaa aaaaaa 0.375 db attenuation steps 0.75 db attenuation steps monotonicity for 1.5 db attenuation steps figure 17. accuracy specification for c grade devices at t a = +25 c
ad7112 rev. 0 C10C microprocessor interfacing figures 18 to 20 show interfaces between the ad7112 and three popular 8-bit microprocessor systems, the mc68008, 8085a/8088 and the 8051. in the mc68008 and 8085/8088 in- terfaces, the ad7112 is memory mapped with separate ad- dresses for each dac. ad7112-8085a/8088 interface figure 18 shows a connection diagram for interfacing the ad7112 to both the 8085a and the 8088 microprocessors. this scheme is also suited to the z80 microprocessor, but the z80 address/data bus does not have to be demultiplexed. the ad7112 is memory mapped with separate memory addresses for dac a and dac b. 8085a / 8088 ad7112* cs wr db7 ?db0 data bus a15 ?a8 ad7 ?ad0 ale address bus wr den dac a / dac b a ** a+1** address decode logic 8-bit latch * analog circuitry has been omitted for clarity. ** a = decoded address for ad7112 dac a a+1 = decoded address for ad7112 dac b figure 18. ad7112C8085a/8088 interface circuit ad7112C68008 interface figure 19 shows a connection diagram for interfacing the ad7112 to the 68008 microprocessor. the ad7112 is again memory mapped with separate memory addresses for dac a and dac b. ad7112* cs wr db7 ?db0 data bus address bus dac a / dac b a ** a+1** address decode logic * analog circuitry has been omitted for clarity. ** a = decoded address for ad7112 dac a a+1 = decoded address for ad7112 dac b 68008 a23 ?a1 d7 ?d0 r /w as dtack figure 19. ad7112C68008 interface circuit ad7112C8051 interface figure 20 shows a connection diagram between the ad7112 and the 8051 microprocessor. the ad7112 is port mapped in this interface. the loading structure is as follows: data to be loaded to the dac is output to port 1: p3.0, p3.1 and p3.2 are bit addressable port lines and are used to control the dac sele ct, cs and wr inputs. a sample routine for writing to dac a is shown below. mov a,data; data to be written is loaded to the accumulator. clr 3.2; select dac a. clr 3.0; bring cs low. clr 3.1; bring wr low. mov a,p1; write data to dac. set b 3.1; deactivate wr . set b 3.0; deactivate cs 8051 p3.0 p3.1 p3.2 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 ad7112* cs wr dac a / dac b db0 db1 db2 db3 db4 db5 db6 db7 * analog circuitry omitted for clarity figure 20. ad7112C8051 interface circuit applications automatic gain control in an automatic gain control system an input signal is attenuated or amplified so that its average output level remains constant. the ad7112 d/a converter is used here as a variable gain or at- tenuation element that adjusts the output signal relative to the input level. a feedback loop consisting of a detector, comparator, and up/ down counter continuously adjusts the contents of the counter and hence the gain or attenuation of the circuit so that the signal level at the output remains constant and equal to the reference input signal. the negative feedback action of the loop ensures that the average output voltage of the automatic gain control system remains constant. figure 21 shows a block diagram of a typical agc control loop using 1/2 ad7112 as the gain/ attenu- ation element. whenever the input signal is outside the dynamic range of the programmable gain element in the agc loop, there should be a stable, well defined input output relationship.
ad7112 rev. 0 C11C output input variable gain element 1/2 ad7112 d up/down counter u v ref end stop and control logic detector comparator figure 21. automatic gain control system programmable state variable filter the ad7112 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications. the circuit of figure 22 shows its use in a state variable filter design. this type of filter has three outputs: low pass, bandpass and high pass. the particular version shown in figure 22 uses two ad7112 to control the critical parameters f 0 , q and a 0 . in- stead of several fixed resistors, the circuit uses the dac equiva- lent resistances as circuit elements. thus, r1 in figure 22 is controlled by the 8-bit word loaded to dac a1 of the ad7112. this is also the case with r2, r3 and r4. dac equivalent resistance, r eq = r dac 10 exp (0.375 n /20) where: r dac is the dac ladder resistance. n is the dac code in decimal (0 n 240). dacs a1 and b1 control the gain and q of the filter character- istic while dacs a2 and b2 control the cutoff frequency. circuit equations: c1 = c2, r3 = r4, r7 = r8. resonant frequency, f 0 = 1/(2 p r3c1). quality factor, q = (r6/r8) (r2/r fbb1 ). r fbb1 is the feedback resistance of dac b1 in figure 22 bandpass gain, a 0 = Cr2/r1. programmable range for component values shown is f 0 = 0 khz to 15 khz and q = 0.3 to 4.5. data 2 out a ad7112 dac a1 (r1) v in a r fb b c3 10pf v in notes 1. a1, a2, a3, a4 : 1/4 x ad713 2. c3 is a compensation capacitor to eliminate q and gain variations caused by amplifier gain bandwidth limitations high pass output out b dac b1 (r2) bandpass output v in b low-pass output r7 30k w r8 30k w r6 10k w c1 1000pf c2 1000pf r5 db0?b7 cs wr dac a/ dac b data 1 dac a2 (r3) dac b2 (r4) a1 out a ad7112 v in a out b v in b db0?b7 cs wr dac a/ dac b a2 a3 a4 figure 22. programmable state variable filter
ad7112 rev. 0 C12C outline dimensions dimensions shown in inches and (mm). 20-pin plastic dip (n-20) 0.280 (7.11) 0.240 (6.10) 1.060 (26.90) 0.925 (23.50) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) pin 1 10 1 11 20 0.210 (5.33) max seating plane 20-pin soic (r-20) 0.0500 (1.27) bsc 0.0192 (0.49) 0.0138 (0.35) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) 0.0157 (0.40) 0.1043 (2.65) 0.0926 (2.35) 0.0125 (0.32) 0.0091 (0.23) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) 0.5118 (13.00) 0.4961 (12.60) 1 10 20 11 pin 1 0 ? 8 ? 0.0291 (0.74) 0.0098 (0.25) x 45 c1692C10C7/92 printed in u.s.a.

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